This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-375482, filed Dec. 28, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor memory and, more particularly, to an electrically erasable and programmable ROM (to be referred to as an EEPROM hereinafter) having NAND memory cells.
EEPROMs are conventionally known as one type of semiconductor memories. Of these EEPROMs, a NAND cell type EEPROM in which a plurality of memory cells are connected in series to form a NAND memory cell is attracting attention as a device which can be highly integrated.
One memory cell in this NAND cell type EEPROM has a MOSFET structure in which a floating gate (a charge storage layer) and a control gate are stacked via an insulating film on a semiconductor substrate. A plurality of such memory cells are connected in series to form a NAND cell such that adjacent memory cells share the source and drain. Such NAND cells are arrayed in a matrix manner to form a memory cell array.
Memory cell arrays are integrated in a p-type-well formed on a p-type-substrate. An n-type-well is first formed on the p-type-substrate, and then the p-type-well for integrating memory cell arrays is formed in this n-type-well.
Drains on the one-end side of a plurality of memory cell arrays arranged in the column direction are connected together to a bit line via select transistors. Sources on the other-end side are connected to a common source line (reference voltage line) via select transistors. The control gates of memory cell transistors are connected to word lines. The gates of the select transistors are connected to select lines.
The operation of this NAND EEPROM will be described below by taking a device in which n-channel transistors are used as memory cell transistors as an example.
Data programming is performed as follows. Data is written in turn from a memory cell farthest from the bit line. A high voltage Vpp (about 20 V) is applied to the control gate of a selected memory cell. An intermediate voltage VppM (about 10 V) is applied to the control gates of memory cells and the gate of the select transistor closer to the bit line than the selected memory cell. The bit line is given a predetermined voltage in accordance with the data, e.g., given 0 V when the data is xe2x80x9c0xe2x80x9d and an intermediate voltage when the data is xe2x80x9c1xe2x80x9d. The power supply voltage is applied to the select line on the bit line side, and the ground voltage is applied to the select line on the source line side. In this state, the voltage of the bit line is transmitted to the drain of the selected memory cell through the select transistor and unselected memory cells.
When 0 V is applied to the bit line (when write data exists, i.e., when data is xe2x80x9c1xe2x80x9d), this voltage is transmitted to the drain of the selected memory cell to apply a high electric field between the gate and drain of the selected memory cell. Hence, electrons are injected (tunnel-injected) from the drain (substrate) into the floating gate. Consequently, the threshold voltage of the selected memory cell shifts in the positive direction.
On the other hand, when the intermediate voltage is applied to the bit line (when no data to be written exists, i.e., when data is xe2x80x9c1xe2x80x9d), no electron injection occurs, so the threshold voltage remains unchanged, i.e., negative.
Data erase is performed as follows.
First, in a selected NAND cell block, the ground voltage is applied to the control gates of all memory cells in the block. In an unselected NAND cell block, the control gates of all memory cells in the block and all select lines, bit lines, and source lines are floating. Subsequently, a high erase voltage (about 20 V) is applied to p- and n-type-wells. Consequently, electrons are emitted into the wells from the floating gates of the memory cells in the selected block, erasing the data in the memory cells in the block.
In this state, the control gates of the memory cells, select lines, bit lines, and source lines in the unselected NAND cell block raise their voltages close to the erase voltage by capacitive coupling. For example, the voltage of the select line rises close to the erase voltage (about 20 V) by the capacitive coupling of the gate capacitance of the select transistor with the other parasitic capacitance in the select line.
Data read is performed as follows.
First, the control gate of a selected memory cell is set at 0 V, and the control gates of other memory cells and the select lines are set at a read voltage (about 3.5 V), thereby turning on unselected memory cell transistors and select transistors. Each data of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d is discriminated by sensing whether a current flows or not into the bit line respectively.
As described above, different voltages are supplied to the select lines and the word lines connected to the control gates in the data programming, erase, and read modes.
FIG. 1 shows a circuit configuration for supplying voltages to select lines and word lines of NAND cells (of n-th blocks).
Referring to FIG. 1, transistors MN1-0 to MN1-19 are high-breakdown-voltage transistors having a thick gate insulating film. They permit a high voltage to be applied to their nodes. Portions R1 to Rn enclosed by the broken lines indicate row selecting means (row decoders) of blocks C1 to Cn. These blocks C1 to Cn represent memory cell arrays in these blocks. For the sake of simplicity, only one bit line is shown in FIG. 1. It is appreciated that multiple bit lines exist and are known in the art. The circuit configuration will be explained by using the circuit of the first block.
Memory cells MC1 to MC16 are connected in series. One end of a current path of a select transistor SD1 is connected to the drain of the memory cell MC1. One end of a current path of a select transistor SS1 is connected to the source of the memory cell MC16. The other end of the current path of the select transistor SD1 is connected to a bit line BL. The other end of the current path of the select transistor SS1 is connected to a source line SL.
The gate of the select transistor SD1 is connected to a select line SGD1. The gate of the select transistor SS1 is connected to a select line SGS1. Also, the gates of the memory cells MC1 to MC16 are connected to word lines WL1-1 to WL1-16, respectively.
The select line SGD1, which controls select transistor SD1 as it is connected to the bit line BL, is connected to one end of a current path of a transfer transistor MN1-0. The other end of this current path is connected to a select line control circuit 51 via a select line SGD. Each of the word lines WL1-1 to WL1-16 is connected to one end of a current path of a corresponding one of transfer transistors MN1-1 to MN1-16. The other end of each of these current paths is connected to a corresponding one of word line control circuits 52-1 to 52-16 via a corresponding one of control gate lines CG1 to CG16. Furthermore, the select line SGS1, which control select transistor SS1 as it is connected to the source line SL, is connected to one end of a current path of a transfer transistor MN1-17. The other end of this current path is connected to a select line control circuit 53 via a select line SGS.
The select line control circuit 51 supplies a voltage to the select line SGD. The word line control circuits 52-1 to 52-16 supply a voltage to the control gate lines CG1 to CG16. The select line control circuit 53 supplies a voltage to the select line SGS.
The gates of the transfer transistors MN1-0 to MN1-17 are connected together to a gate line G1, and this gate line G1 is connected to a high-voltage transfer circuit 54-1. A high voltage generator 55 supplies a voltage equal to or higher than a power supply voltage Vcc to the high-voltage transfer circuit 54-1 via a transfer line LPIN. An address signal ADDRESS is input to a NAND gate circuit NA51-1. The output from this NAND gate circuit NA51-1 is supplied as a decode signal DEC1 of the address signal to the high-voltage transfer circuit 54-1 via an inverter IV51-1.
The source of a transistor MN1-18 is connected to the select line SGD1. The source of a transistor MN1-19 is connected to the select line SGS1. The drains of these transistors MN1-18 and MN1-19 are connected to a selective driving circuit 56 via a selecting line SGDS. The gates of the transistors MN1-18 and MN1-19 are supplied with the inverted output of the address decode signal, which is the output from the NAND gate circuit NA51-1. In data erase, the selective driving circuit 56 supplies a threshold drop voltage of the power supply voltage VCC to the select lines SGD1 and SGS1. In other cases, the selective driving circuit 56 supplies a ground voltage Vss to the select lines SGD1 and SGS1.
When the block C1 is selected, the high-voltage transfer circuit 54-1 supplies to the gate line G1 a voltage equal to or higher than the power supply voltage and sufficient to turn on the transfer transistors MN1-0 to MN1-17, in accordance with each of the data programming, erase, and read modes. Accordingly, the transfer transistor MN1-0 transfers the output voltage from the select line control circuit 51 to the select line SGD1. The transfer transistors MN1-1 to MN1-16 transfer the output voltages from the word line control circuits 52-1 to 52-16 to the word lines WL1-1 to WL1-16, respectively. Furthermore, the transfer transistor MN1-17 transfers the output voltage from the select line control circuit 53 to the select line SGS1. When the block C1 is not selected, the high-voltage transfer circuit 54-1 applies the ground voltage to the gate line G1. Consequently, the transfer transistors MN1-0 to MN1-17 are cut off.
High-breakdown-voltage transistors are used as the transfer transistors MN1-0 to MN1-17, MN1-18, and MN1-19 because in data erase the voltage of the sources (the select lines or the word lines of unselected blocks) of these transistors rise to about the erase voltage (about 20 V) by capacitive coupling.
FIGS. 2 to 4 are timing charts showing the operations of data programming, read, and erase in the circuit shown in FIG. 1.
Different voltages, i.e., about 20 V for data programming, about 3.5 V for data read, and the power-supply voltage for data erase, are set in the high-voltage source circuit 55. These different voltages are supplied from the high-voltage source circuit 55 to the high-voltage transfer circuit 54-1. This high-voltage transfer circuit 54-1 is controlled by the address decode signal DEC1. When the block C1 is selected, the output from the high-voltage transfer circuit 54-1 is supplied to the gate electrodes of the transfer transistors MN1-0 to MN1-17 via the gate line G1. Consequently, the output voltage from the select line control circuit 51 is transferred to the select line SGD1, and the output voltage from the select line control circuit 53 is transferred to the select line SGS1. Furthermore, the output voltages from the word line control circuits 52-1 to 52-16 are transferred to the word lines WL1-1 to WL1-16, respectively.
When the block C1 is not selected, the high-voltage transfer circuit 54-1 supplies the ground voltage to the gate line G1. Accordingly, the transfer transistors MN1-0 to MN1-17 are cut off, and the select lines SGD1 and SGS1 and the word lines WL1-1 to WL1-16 are floating. In this state, the transfer transistors MN1-18 and MN1-19 are turned on, and the output voltage of the selective driving circuit 56 is supplied to the select lines SGD1 and SGS1.
As has been described above, when the block C1 is selected in the semiconductor memory shown in FIG. 1, different voltages are supplied to the select lines SGD1 and SGS1 and the word lines WL1-1 to WL1-16 in accordance with the data programming, read, and erase modes. The transfer transistors MN1-0 to MN1-17 transfer the voltages to the select lines SGD1 and SGS1 and the word lines WL1-1 to WL1-16. The gate line G1 is connected to the gate electrodes of these transfer transistors MN1-0 to MN1-17. When the block C1 is selected, different voltages are supplied to the gate line G1 in accordance with the data programming, read, and erase modes. On the other hand, if the block C1 is not selected, the ground voltage is supplied to the gate line G1.
Accordingly, when this block C1 switches from an unselected to a selected state and from a selected to an unselected state in these modes, charging for raising from the ground voltage to the operating voltages of these modes and discharging for lowering these operating voltages to the ground voltage are repeatedly performed for the gate line G1. This increases the charge/discharge time of the gate line G1 and consumes a current. Also, the gate electrodes of the transistors for transferring voltages to the select lines SGD1 and SGS1 and the gate electrodes of the transistors for transferring voltages to the word lines WL1-1 to WL1-16 are connected together to the gate line G1. Hence, to transfer a voltage from the select line SGD to the select line SGD1 or from the select line SGS to the select line SGS1, a voltage more than necessary must be supplied.
Furthermore, in data erase the erase voltage (about 20 V) is applied to the substrate or the well. Since this raises the voltages of the select lines SGD1 and SGS1 in a floating state to about the erase voltage (about 20 V) by capacitive coupling, high-breakdown-voltage transistors (low-current-driven transistors) are used as the transfer transistors MN1-0 to MN1-17. In data read and write, the gates of the transfer transistors MN1-0 to MN1-17 are boosted whenever the NAND cell block is selected, so it takes a long time for these transfer transistors to turn on. Also, the transfer transistors MN1-0 to MN1-17 are slow in operation because they are high-breakdown-voltage transistors.
Accordingly, voltages cannot be rapidly transferred to the select lines SGD1 and SGS1 and the word lines WL1-1 to WL1-16. For example, in a 256-Mbit NAND cell type EEPROM, the data read time is determined by the resistance of a transfer transistor connected to a select line, i.e., by the size of the transistor.
Additionally, high-breakdown-voltage transistors (low-current-driven transistors) are also used in the select line control circuits 51 and 53, and these select line control circuits are shared by NAND cells in all blocks. This increases the length of wiring to the transfer transistors MN1-0 to MN1-17, resulting in a large wiring delay. Hence, voltages cannot be rapidly supplied to the select lines SGD1 and SGS1.
The present invention has been made in consideration of the above situation, and has as its object to provide a semiconductor memory capable of suppressing current consumption, rapidly supplying voltages to the gates (select lines) of select transistors, and increasing a access time required for reading data.
To achieve the above object, a semiconductor memory device according to a first aspect of the present invention comprises a memory cell for storing information, a select transistor connected to the memory cell, a select circuit for outputting a first signal for selecting the memory cell, a select line connected the gate of the select transistor, a select line control circuit for driving the select transistor, the select line control circuit outputting a second signal in accordance with the first signal and a operation mode of the memory cell, a first transistor having a current path whose one end is connected to the select line control circuit and other end is connected to the gate of the select transistor, the first transistor transferring the second signal to the select line, a first gate line connected to the gate of the first transistor, a first voltage control circuit for supplying a voltage to the first gate line to turn on or off the first transistor, a word line control circuit for driving a word line connected to the gate of the memory cell, the word line control circuit outputting a third signal, a second transistor having a current path whose one end is connected to the word line control circuit and other end is connected to the word line, the second transistor transferring the third signal to the word line, a second gate line connected to the gate of the second transistor, the second gate line being disconnected from the first gate line, and a second voltage control circuit for supplying a voltage to the second gate line to turn on or off the second transistor.
To achieve the above object, a semiconductor memory device according to a second aspect of the present invention comprises a memory cell array in which memory cell blocks are arrayed in a column direction, each of the memory cell blocks being formed by arranging memory cell units in a row direction, and each of the memory cell units being formed by connecting a select transistor to a memory cell for storing information, a select circuit for outputting a first signal for selecting each of the memory cell blocks, a select line connected the gate of the select transistor, a select line control circuit for driving the select transistor, the select line control circuit outputting a second signal in accordance with the first signal and a operation mode of the memory cell, a first transistor having a current path whose one end is connected to the select line control circuit and other end is connected to the gate of the select transistor, the first transistor transferring the second signal to the select line, a first gate line connected to the gate of the first transistor, a first voltage control circuit for supplying a voltage to the first gate line to turn on or off the first transistor, a word line control circuit for driving a word line connected to the gate of the memory cell in the memory cell unit, the word line control circuit outputting a third signal, a second transistor having a current path whose one end is connected to the word line control circuit and other end is connected to the word line, the second transistor transferring the third signal to the word line, a second gate line connected to the gate of the second transistor, the second gate line being disconnected from the first gate line, and a second voltage control circuit for supplying a voltage to the second gate line to turn on or off the second transistor.
To achieve the above object, a semiconductor memory device according to a third aspect of the present invention comprises a memory cell array in which memory cell units are arrayed in a matrix manner, each of the memory cell units being formed by connecting select transistors to two ends of one memory cell transistor for storing information, a bit line being connected to a select transistor connected to one end of the memory cell unit, and a source line being connected to a select transistor connected to the other end of the memory cell unit, a select circuit for outputting a first signal for selecting each of the memory cell units arrayed in a row direction, a select line connected each of the gates of the select transistors, a select line control circuit for driving at least one of the select transistors, the select line control circuit outputting a second signal in accordance with the first signal and a operation mode of the memory cell, a first transistor having a current path whose one end is connected to the select line control circuit and other end is connected to the gate of at least one of the select transistors, the first transistor transferring the second signal to the select line, a first gate line connected to the gate of the first transistor, a first voltage control circuit for supplying a voltage to the first gate line to turn on or off the first transistor, a word line control circuit for driving a word line connected to the gate of the memory cell in each of the memory cell units arrayed in the row direction, the word line control circuit outputting a third signal, a second transistor having a current path whose one end is connected to the word line control circuit and other end is connected to the word line, the second transistor transferring the third signal to the word line, a second gate line connected to the gate of the second transistor, the second gate line being disconnected from the first gate line, and a second voltage control circuit for supplying a voltage to the second gate line to turn on or off the second transistor.
To achieve the above object, a semiconductor memory device according to a fourth aspect of the present invention comprises a memory cell for storing information, a select transistor connected to the memory cell, a select line control circuit for driving the select transistor, a first transistor having a current path whose two ends are connected between the select line control circuit and the gate of the select transistor, a first gate line connected to the gate of the first transistor, a first voltage control circuit for supplying a voltage to the first gate line to turn on or off the first transistor, a word line control circuit for driving a word line connected to the gate of the memory cell, a second transistor having a current path whose two ends are connected between the word line control circuit and the word line, a second gate line connected to the gate of the second transistor, the second gate line being disconnected from the first gate line, and a second voltage control circuit for supplying a voltage to the second gate line to turn on or off the second transistor.
In the semiconductor memories having any of the above arrangements, the gate (first gate line) of the first transistor for transferring voltages to the gate of the select transistor is separated from the gate (second gate line) of the second transistor for transferring voltages to the control gate of the memory cell. Therefore, constant voltages can be supplied to the gate of the first transistor, and the number of times of charge/discharge of the gate of the first transistor can be reduced. Accordingly, it is possible to supply stable voltages to the gate of the first transistor connected to the select line, reduce the load on the booster circuit, reduce current consumption, and rapidly transfer voltages to the gate (select line) of the select transistor. This makes a high-speed operation, particularly a high-speed read operation feasible.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.